Advanced Packaging / Chiplet Layout Engineer
Expression of interest for upcoming mandates. HiredNext is building a specialist talent pool for package-aware chiplet and advanced-interface implementation. This is not presented as a confirmed vacancy with an identified employer.
Profile we want to identify
- 8–15 years in analog or mixed-signal custom layout, package-aware implementation or advanced packaging.
- Experience with UCIe, SerDes or die-to-die PHY layout and successful tape-outs.
- Strong micro-bump planning, bump-map architecture, package-aware floorplanning and parasitic control.
- Exposure to 2.5D/3D integration, interposers, RDL, TSVs or chiplet package co-design.
Location focus
Bengaluru, with relevance to Hyderabad, Noida and emerging semiconductor packaging ecosystems.
Register interest
Apply through the form below or email your CV to jobs@hirednext.info with the subject Semiconductor Talent Pool | Advanced Packaging / Chiplets. HiredNext does not charge candidates to register interest or apply for recruitment mandates.
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