IO / MXS Layout Engineer

Job code: HN-IOMXS-1028

HiredNext Recruitment is managing a confidential search for an IO / MXS Layout Engineer with a semiconductor technology organisation. The employer identity will be shared only with relevant shortlisted candidates.

Location: Bengaluru. Work mode: On-site. Experience: 4–12 years.

Role overview

Work on advanced IO and mixed-signal layout implementation and physical verification for leading-edge semiconductor designs.

Key responsibilities

• Develop and implement IO / mixed-signal layouts using Cadence Virtuoso.
• Handle complex routing, matching, shielding and layout-dependent effects for high-speed and mixed-signal blocks.
• Perform DRC, LVS and physical-verification closure using Calibre.
• Address EM/IR, parasitic, signal-integrity and power-integrity considerations as relevant to the block.
• Collaborate with circuit-design, verification and physical-design teams through sign-off.
• Support layout quality, manufacturability and tapeout readiness on advanced process nodes.

Required skills & qualifications

• 4–12 years of relevant IO / MXS or mixed-signal layout experience.
• Strong hands-on expertise with Cadence Virtuoso.
• Strong experience with Calibre DRC / LVS and physical-verification flows.
• Good understanding of parasitic effects, matching, routing, EM/IR and layout-dependent effects.
• Strong debugging and problem-solving capability.
• Experience working with cross-functional semiconductor design teams.

Preferred technology exposure

• TSMC: A14n, 2nm, 3nm, 5nm.
• Samsung: 2nm, 4nm.

There are multiple requirements across IO / MXS Layout and Memory Layout.

How to apply

Apply through the form below or email your CV to jobs@hirednext.info with the subject HN-IOMXS-1028 | IO / MXS Layout Engineer.

The employer identity will be shared only with relevant shortlisted candidates. HiredNext does not charge candidates to apply for a role or secure placement.