DFT Engineer – SoC / Scan / ATPG

Expression of interest for upcoming mandates. HiredNext is curating a niche semiconductor pipeline for experienced Design for Test professionals. This is not presented as a confirmed vacancy with an identified employer.

Profile we want to identify

• 6–10 years of DFT experience on complex SoCs or large digital designs.
• Strong scan insertion, ATPG, test coverage, diagnosis and debug experience.
• Exposure to production test readiness and silicon bring up is highly relevant.
• Working knowledge of established DFT tool flows from Synopsys, Cadence, Siemens Tessent or comparable environments.
• Ability to work closely with RTL, verification, physical design and validation teams.

Location focus

Hyderabad, with flexibility for relevant semiconductor opportunities in Bengaluru and Noida.

Register interest

Use the application form below or email your CV to jobs@hirednext.info with the subject Semiconductor Talent Pool | DFT Engineer. HiredNext does not charge candidates to register interest or apply for recruitment mandates.